1. Field of the Invention
Generally, the present disclosure relates to the fabrication of integrated circuits, and, more particularly, to transistors having strained channel regions by using embedded silicon/germanium (Si/Ge) and the like so as to enhance charge carrier mobility in the channel regions of the transistors.
2. Description of the Related Art
The fabrication of complex integrated circuits requires a large number of transistor elements, which represent the dominant circuit element for complex circuits, to be formed in a die region. For example, several hundred million transistors may be provided in presently available complex integrated circuits. Generally, a plurality of process technologies are currently practiced, wherein, for complex circuitry, such as microprocessors, storage chips and the like, CMOS technology is currently the most promising approach due to the superior characteristics in view of operating speed and/or power consumption and/or cost efficiency. In CMOS circuits, complementary transistors, i.e., P-channel transistors and N-channel transistors, are used for forming circuit elements, such as inverters and other logic gates to design highly complex circuit assemblies. During the fabrication of complex integrated circuits using CMOS technology, transistors, i.e., N-channel transistors and P-channel transistors, are formed on a substrate including a crystalline semiconductor layer. A MOS transistor or generally a field effect transistor, irrespective of whether an N-channel transistor or a P-channel transistor is considered, comprises so-called PN junctions that are formed by an interface of highly doped drain and source regions with an inversely or weakly doped channel region disposed between the drain region and the source region. The conductivity of the channel region, i.e., the drive current capability of the conductive channel, is controlled by a gate electrode formed in the vicinity of the channel region and separated therefrom by a thin insulating layer. The conductivity of the channel region, upon formation of a conductive channel due to the application of an appropriate control voltage to the gate electrode, depends on, among other things, the dopant concentration, the mobility of the charge carriers and, for a given extension of the channel region in the transistor width direction, on the distance between the source and drain regions, which is also referred to as channel length. Thus, the reduction of the channel length, and associated therewith the reduction of the channel resistivity, is a dominant design criterion for accomplishing an increase in the operating speed of the integrated circuits.
The continuing shrinkage of the transistor dimensions, however, involves a plurality of issues associated therewith that have to be addressed so as to not unduly offset the advantages obtained by steadily decreasing the channel length of MOS transistors. For example, highly sophisticated dopant profiles, in the vertical direction as well as in the lateral direction, are required in the drain and source regions so as to provide low sheet and contact resistivity in combination with desired channel controllability. Moreover, the gate dielectric material may also be adapted to the reduced channel length in order to maintain the required channel controllability. However, some mechanisms for maintaining high channel controllability may also have a negative influence on the charge carrier mobility in the channel region of the transistor, thereby partially offsetting the advantages gained by the reduction of the channel length.
Since the continuous size reduction of the critical dimensions, i.e., the gate length of the transistors, necessitates the adaptation and possibly the new development of highly complex process techniques and may also contribute to less pronounced performance gain due to mobility degradation, it has been proposed to enhance the channel conductivity of the transistor elements by increasing the charge carrier mobility in the channel region for a given channel length, thereby enabling a performance improvement that is comparable with the advance to a technology standard that would require extremely scaled critical dimensions, while avoiding or at least postponing many of the process adaptations associated with device scaling.
One efficient mechanism for increasing the charge carrier mobility is the modification of the lattice structure in the channel region, for instance by creating tensile or compressive stress in the vicinity of the channel region so as to produce a corresponding strain in the channel region, which results in a modified mobility for electrons and holes, respectively. For example, creating tensile strain in the channel region for a standard crystallographic configuration of the active silicon material, i.e., a (100) surface orientation with the channel length aligned to the <110> direction, increases the mobility of electrons, which, in turn, may directly translate into a corresponding increase in conductivity. On the other hand, compressive strain in the channel region may increase the mobility of holes, thereby providing the potential for enhancing the performance of P-type transistors. The introduction of stress or strain engineering into integrated circuit fabrication is an extremely promising approach, since strained silicon may be considered as a “new” type of semiconductor material, which may enable the fabrication of fast powerful semiconductor devices without requiring expensive semiconductor materials, while many of the well-established manufacturing techniques may still be used.
Consequently, it has been proposed to introduce, for instance, a silicon/germanium material next to the channel region so as to induce a compressive stress that may result in a corresponding strain. When forming the silicon/germanium material, the drain and source regions of the PMOS transistors are selectively recessed to form cavities, while the NMOS transistors are masked, and subsequently the silicon/germanium material is selectively formed in the cavities of the PMOS transistor by epitaxial growth.
Although the technique has significant advantages in view of performance gain of P-channel transistors and thus of the entire CMOS device, it turns out, however, that, in advanced semiconductor devices including a large number of transistor elements, an increased variability of device performance may be observed, which may be associated with the above-described technique for incorporating a strained silicon/germanium alloy in the drain and source regions of P-channel transistors.
The presence of a strain-inducing silicon/germanium material in the drain and source regions of P-channel transistors may drastically alter the current drive capability of the transistor and, thus, even small variations during the incorporation of the silicon/germanium material or any variations of the material composition may, therefore, significantly affect performance of the P-channel transistors. The strain-inducing effect of the embedded silicon/germanium material depends on the amount of the embedded strain-inducing semiconductor material, the distance with respect to the channel region and also depends on the size and shape of the strain-inducing semiconductor material. For example, incorporating an increased fraction of germanium may result in an increase of the resulting strain, since the corresponding lattice mismatch between the silicon/germanium material and the silicon material of the active region may be increased. The maximum concentration of germanium in the semiconductor alloy, however, may depend on the process strategy used, since further increasing the germanium concentration may result in undue germanium agglomeration, which in turn may provide increased lattice defects and the like. Furthermore, the amount of the strain-inducing material and the shape thereof in the drain and source regions may depend on the size and shape of the cavities formed in the drain and source areas, wherein also the effective distance from the channel region may be substantially determined on the basis of the size and shape of the corresponding cavities.
A typical conventional process flow for forming an embedded silicon/germanium material in P-channel transistors may include the following process steps. After forming the active semiconductor regions, which is typically accomplished by forming appropriate isolation regions that laterally delineate the active regions, the electrode structures are formed on the basis of any appropriate process strategy. That is, appropriate materials, such as dielectric materials, electrode materials and the like, are provided in combination with one or more appropriate dielectric cap materials which may be used, in addition to its use in the actual patterning of the gate layer stack, as an etch and deposition mask in a later manufacturing stage when the embedded strain-inducing silicon/germanium material is deposited. In sophisticated applications, the gate electrode structures of field effect transistors are provided with a gate length of 50 nm and less thereby providing superior transistor performance, for instance in terms of switching speed and drive current capability. The reduced critical dimensions, however, may also contribute to a pronounced dependency of the resulting transistor performance on process variations, in particular when any such process variations may occur upon implementing a very efficient performance enhancing mechanism, such as embedding the strain-inducing silicon/germanium material in P-channel transistors. For example, a variation of the lateral distance of the silicon/germanium material with respect to the channel region may over-proportionally influence the finally obtained performance, in particular when basically extremely scaled transistors are considered.
Based on the dielectric cap material and the sidewall spacer structure, cavities may then be etched in to the drain and source areas, wherein the size and shape may be substantially determined on the basis of the etch parameters of the corresponding etch process. It should be appreciated that any other transistors, such as N-channel transistors, in which the incorporation of a silicon/germanium material is not required, are covered by an appropriate mask layer. After any appropriate cleaning processes for preparing exposed surface areas of the silicon material in the drain and source areas, a selective epitaxial growth process may be performed, in which the silicon/germanium material may be selectively deposited on exposed silicon surface areas while a significant deposition of the semiconductor material on dielectric surface areas, such as dielectric cap materials, sidewall spacers, isolation regions and mask layers, may be suppressed.
As discussed above, the final gain in performance of the P-channel transistor transistors may depend critically on the amount of strained semiconductor material and its offset from the channel region. Consequently, great efforts have been made in developing a process strategy in which a plurality of complex processes may be performed on the basis of a degree of process uniformity across the individual semiconductor die regions and also across entire substrates to reduce any variability of the transistor characteristics.
It is well known that a plurality of processes, such as plasma assisted etch processes, deposition processes and the like, may be influenced by the local configuration of the substrate surface to be treated. That is, the etch rate in plasma assisted etch processes may be influenced by the “pattern” density, i.e., by the ratio of surface area to be etched with respect to the surface area of substantially resistive materials. For example, when a large number of densely packed active areas may have to be provided with corresponding cavities, the resulting etch rate in this device area may differ from an etch rate in an area in which a moderate number of more or less isolated active regions may have to be etched. The corresponding effect is also known as “pattern loading.” Similarly, the deposition rate may vary to a certain degree depending on the local pattern density, wherein, for instance, in selective epitaxial growth recipes for forming silicon/germanium, an increased fill behavior in densely packed device areas may be observed compared to more or less isolated device regions, while in other cases the opposite deposition behavior may occur.
Consequently, it is very difficult to adjust the process parameters of the selective epitaxial growth process in such a manner that a substantially uniform fill height of the silicon/germanium alloy is accomplished across the entire die region. Moreover, upon attempting to achieve a substantially uniform fill height across the substrate, nevertheless the local fill conditions may be different within individual active regions, for instance when filling a cavity that is adjacent to an isolation region, since typically the material deposition on dielectric surface areas is significantly restricted during the selective epitaxial growth process. Thereafter, different fill behaviors may be observed in a highly local manner, for instance by achieving a substantially bottom-to-top fill behavior, while in other cases pronounced facets may be achieved at an interface between a dielectric material and the selectively grown silicon/germanium alloy. Therefore, a plurality of process-related non-uniformities may be introduced, which may finally result in a pronounced transistor variability, in particular when highly scaled sophisticated high-k metal gate electrode structures are considered. As discussed above, although the fabrication of the sophisticated high-k metal gate electrode structures in an early manufacturing phase may provide substantial advantages compared to a replacement gate approach, the complex interaction of the various process-related non-uniformities may finally result in severe device failures, as will be explained in more detail with reference to FIGS. 1a-1g. 
FIG. 1a schematically illustrates a cross-sectional view of a semiconductor device 100 in a manufacturing stage in which complex high-k metal gate electrode structures 160A, 160B, 160C may be provided with lateral dimensions of, for instance, 50 nm and less. In this manufacturing stage, the device 100 typically comprises a substrate 101 in combination with a semiconductor layer 102, such as a silicon layer, in which a plurality of active regions are provided, wherein, for convenience, a first active region 102A, representing the active region of P-channel transistors, and a second active region 102C are illustrated. Generally, an active region is to be understood as a semiconductor region of the layer 102 in and above which one or more transistors have to be formed. The active regions 102A, 102C are laterally delineated by an appropriately dimensioned and shaped isolation structure 102B, for instance, provided in the form of a shallow trench isolation. As shown, the gate electrode structures 160A, 160B may represent gate electrode structures of P-channel transistors to be formed in and above the active region 102A, while the gate electrode structure 160C represents the gate electrode structure of an N-channel transistor to be formed in and above the active region 102C. In the manufacturing stage shown, the gate electrode structures 160A, 160B, 160C comprise a gate dielectric material 161, which may have incorporated therein a gate dielectric material so as to provide a total dielectric constant that is 10.0 and higher, which may be accomplished on the basis of materials such as hafnium oxide, zirconium oxide and the like, which are generally referred to hereinafter as high-k dielectric materials. Furthermore, a metal-containing electrode material 162, such as titanium nitride and the like, is typically provided in combination with the dielectric material 161 in order to obtain the required threshold voltage characteristics and the like. It should be noted, however, that the materials 161, 162 in the gate electrode structures 160A, 160B on the one hand, and in the gate electrode structure 160C on the other hand, may differ in their material composition, for instance with respect to a work function metal species since typically different work functions are required for the gate electrode structures of different transistors. Furthermore, a silicon-based electrode material 163 is provided in combination with a dielectric cap layer or cap layer system 164, for instance comprising silicon nitride, silicon dioxide and the like. Furthermore, a spacer structure 165, for instance comprised of one or more silicon nitride layers and the like, are formed on sidewalls of the electrode material 163 and the sensitive materials 162, 161 in the gate electrode structures 160A, 160B, while a spacer layer 165S is provided so as to cover the second active region 102C and the gate electrode structure 160C. Additionally, an etch mask 103, such as a resist mask, is formed above the second active region 102C.
The device 100 as shown in FIG. 1a may be formed on the basis of the following process strategy. The isolation structure 102B is formed by applying sophisticated lithography, etch, deposition, anneal and planarization techniques in order to form trenches and fill the trenches with an appropriate dielectric material, thereby also defining the lateral size and shape of the active regions 102A, 102C. After incorporating any dopant species in accordance with the overall device requirements, the gate electrode structures 160A, 160B, 160C are formed, which may require complex deposition and patterning processes in order to provide the materials 161, 162 for the various transistor types. That is, since typically different work function metal species have to be provided for different transistor types, a corresponding deposition, masking and patterning regime is applied in this manufacturing stage, possibly followed by any thermal treatments in order to provide the materials 161 and 162 with the required characteristics. Thereafter, the electrode material 163 in combination with the cap material or materials 164 are deposited and subsequently patterned by using sophisticated lithography and etch strategies, thereby finally obtaining the gate electrode structures 160A, 160B, 160C with the desired critical dimensions, i.e., with a gate length 160L of 50 nm and significantly less in sophisticated applications. Next, the spacer layer 165S is deposited, which may include one or more deposition processes, such as a multi-layer deposition, possibly in combination with a low pressure chemical vapor deposition (CVD) process, followed by the patterning of the etch mask 103, which may then be used for etching the spacer layer 165S in order to obtain the spacer elements 165 in the gate electrode structures 160A, 160B. It should be appreciated that the spacer structures 165 are used for confining the sensitive gate materials and may also act as offset spacer elements during the further processing for forming cavities in the active region 102A and for appropriately defining the lateral and vertical dopant profiles in the active regions 102A, 102C in a further advanced manufacturing stage. Due to the patterning process of the spacer layer 165S, generally a certain degree of material erosion may occur in exposed portions of the isolation structure 102B and the exposed cap layers 164, as well as in the active region 102A, as indicated by the dashed line.
FIG. 1b schematically illustrates the device 100 in an advanced manufacturing stage in which cavities 104 are formed in the active region 102A, which is typically accomplished by applying an anisotropic plasma assisted etch process, which, in some illustrative embodiments, is performed as an in situ process upon patterning the spacer layer 165S. Due to the anisotropic nature of the etch process, the resulting cavities 104 are substantially U-shaped, wherein the depth of the cavity strongly depends on the process parameters of the corresponding plasma assisted etch process. After the etch process, the mask 103 (FIG. 1a) may be removed, thereby exposing the spacer layer 165S. Thereafter, the device 100 is prepared for the subsequent selective deposition of a silicon/germanium alloy in the cavities 104, which may involve a plurality of cleaning recipes and the like.
FIG. 1c schematically illustrates the device 100 in a further advanced stage in which a silicon/germanium material 105 is selectively grown in the cavities 104, while the spacer layer 165S may be used as a deposition mask above the active region 102C. As explained above, a selective epitaxial growth process may, in addition to the pattern loading effects discussed above, suffer from a very local deposition related non-uniformity, for instance at sidewall surfaces 102S of the isolation structure 102B. Frequently, a facet-like configuration is obtained during the growth of the material 105, thereby creating respective “shoulders” 105S at the edge of the peripheral cavities 104, while in the central cavity a substantially uniform growth of the material 105 is observed.
After the growth of the material 105, the spacer layer 165S may be patterned into the spacer structure 165 in the gate electrode structure 160C, wherein the active region 102A may be covered by a resist mask (not shown), while in other cases a corresponding material erosion in the cap layers 164 of the gate electrode structures 160A, 160B and also in the silicon/germanium alloy 105 may be observed.
FIG. 1d schematically illustrates the device 100 in a further advanced manufacturing stage in which a process strategy is applied that requires the subsequent removal of the cap layers 164 while preserving the spacer structure 165 so as to ensure integrity of the sensitive gate materials and also enable the usage of the spacer structure 165 as an offset spacer structure during the further processing, for instance when incorporating drain and source dopant species. In order to substantially preserve the spacer structure 165, sacrificial spacer elements 106, for instance comprised of silicon dioxide, are formed, which is accomplished by depositing an appropriate oxide material and patterning the same on the basis of a plasma assisted etch process. Consequently, during the corresponding etch process, an additional erosion of the material 105 is observed, as indicated by 105E, while also a certain material loss in the isolation structure 102B may be observed.
FIG. 1e schematically illustrates the device 100 after performing a further etch process, for instance on the basis of appropriate wet chemical etch recipes, such as hot phosphoric acid and the like so as to remove the dielectric cap layers 164 (FIG. 1d), thereby exposing the silicon-based electrode material 163 in the gate electrode structures 160A, 160B, 160C. During the corresponding etch process, however, a further erosion, in particular of the material 105, may be observed so that, in total, up to one third of the initially deposited silicon/germanium alloy may be lost. In particular, the pronounced shoulders 105S may have a significant influence on the finally obtained transistor characteristics and also on increased yield losses in a later manufacturing stage.
FIG. 1f schematically illustrates the device 100 in a further advanced manufacturing stage. As shown, transistors 150A, 150B are formed in and above the active region 102A on the basis of the gate electrode structures 160A, 160B. Similarly, a transistor 150C is formed in and above the active region 102C and comprises the gate electrode structure 160C. The transistors 150A, 150B are P-channel transistors and thus the performance thereof significantly depends on the strain-inducing effect within a channel region 152 induced by the previously grown semiconductor material 105. Thus, due to the pronounced shoulders 105S and due to the pronounced material loss of the material 105 during the further processing, as explained above, the finally achieved strain in the channel regions 152 of the transistors 150A, 150B may generally be reduced and may also be highly non-uniform, for instance with respect to the difference of the material 105 formed immediately adjacent to isolation regions 202B compared to the material 105 formed in a central area of the active region 102A. For example, if more than two transistors are formed in the active region 102A, central transistors may have very different performance characteristics compared to any “edge” transistors, which are provided adjacent to an isolation region.
Furthermore, the transistors 150A, 150B and 150C comprise drain and source regions 151 having any appropriate lateral and vertical dopant profile, wherein it should be appreciated that the drain and source regions 151 in the active region 102A are of inverse conductivity type compared to the drain and source regions 151 in the active region 102C. The dopant profile of the drain and source regions 151 may be adjusted on the basis of a spacer structure 167, possibly in combination with the spacer structure 165, wherein also the pronounced shoulders 105S may contribute to process non-uniformities upon forming the spacer structure 167 due to a significant difference between central areas and peripheral areas of the active region 102A.
Furthermore, metal silicide regions 156 may be provided in the drain and source regions, wherein, due to the disadvantageous shape and configuration of the shoulders 105S, generally a reduced thickness of the metal silicide 156 in these areas is observed compared to the central metal silicide 156 and compared to the metal silicide 156 in the transistor 150C. The non-uniformity in thickness of the metal silicide material in the drain and source regions 151 of the transistors 150A, 150B may have a remarkable influence on device failures upon forming contact elements in a later manufacturing stage. Furthermore, metal silicide material 166 may be formed in the gate electrode structures 160A, 160B, 160C, thereby also providing superior conductivity of the gate electrode structures.
The transistors 150A, 150B, 150C may be formed on the basis of any appropriate process strategy for incorporating the drain and source dopant species and forming the spacer structure 167, wherein, as discussed above, the pronounced surface non-uniformity of the shoulders 105S may result in a non-uniform spacer width, which in turn may cause non-uniformities in the drain and source regions of “edge” transistors compared to central transistors. After any anneal processes, the metal silicide materials 156, 166 are formed, for instance, by using well-established process strategies for depositing one or more desired refractory metals, such as nickel, platinum and the like, and initiating a chemical reaction, wherein the metal silicide thickness at the shoulders 105S may be reduced.
FIG. 1g schematically illustrates the device 100 in a further advanced manufacturing stage in which a contact level 120 is formed so as to enclose and passivate the transistors 150A, 150B, 150C. The contact level 120 may comprise the first dielectric material 121, such as a silicon nitride material, followed by a second dielectric material 122, such as a silicon dioxide material and the like. To this end, any well-established deposition recipes are typically applied. After planarizing the dielectric materials, sophisticated patterning regimes are applied in order to form openings 123 in the dielectric materials 122, 121, wherein, in a final etch step, typically the metal silicide 156 in the drain and source regions 151 is used as an etch stop material. Due to the reduced thickness in the “edge” transistors caused by the shoulders 105S, the etch stop capabilities may be significantly reduced so that the etch process may etch through the metal silicide material 156 and deeply into the active region 102A which, upon filling the contact openings 123 with a conductive material, may result in a short-circuiting of the drain and source regions 151, thereby at least significantly altering the transistor characteristics or even contributing to a total device failure.
Consequently, the plurality of complex process steps involved in providing a strain-inducing semiconductor alloy in sophisticated transistors may thus result in pronounced transistor variability and significant yield losses.
In view of the situation described above, the present disclosure relates to manufacturing techniques and semiconductor devices in which a strain-inducing semiconductor alloy may be incorporated into the active region, in particular for transistors comprising sophisticated high-k metal gate electrode structures, while avoiding, or at least reducing, the effects of one or more of the problems identified above.